1. Field of the Invention
The present invention relates to an arithmetic operation circuit, and more particularly to an arithmetic circuit capable of executing both of a floating point arithmetic operation and a fixed point arithmetic operation.
2. Description of Related Art
One-chip integrated electronic circuits such as one-chip microcomputers which can perform arithmetic operation are demanded to be capable of executing a complicated operation such as a floating point arithmetic operation with an increasing scale of integrated circuits. The floating point arithmetic operation is widely utilized mainly for the purpose of extending the range of numerical data representable with a limited number of bits, and for the purpose of automatically correcting an overflow resulting from an arithmetic operation.
In the floating point arithmetic operation, a numerical data is expressed by the exponent and the fraction or mantissa, and the exponent and the fraction of given numerical data is separately processed.
Accordingly, a conventional typical floating point arithmetic circuit comprises a pair of input registers adapted to temporarily hold a pair of given floating point representation numbers to be operated, respectively. The pair of numbers stored in the pair of registers are fed to a radix point adjustment circuit so that the radix points of the given numbers are aligned when addition or subtraction should be executed. In other words, the pair of given floating point numbers are converted into another pair of floating point numbers which have the same value in their respective exponent portions but still represent the same numbers as those indicated by the original given floating point numbers, respectively.
The respective fraction portions of the thus obtained floating point numbers having the same value of exponent are inputted to a pair of input ports of a fraction operating circuit. This fraction operating circuit outputs the result of a given arithmetic operation of the inputted fraction numbers to a fraction correction circuit, and generates an overflow signal when an overflow occurs as the result of the arithmetic operation. The fraction correction circuit outputs the input fraction number as it is to a fraction portion of an output register when the overflow signal is not generated. But, when the overflow signal is generated, the fraction correction circuit right-shifts the input fraction number by one bit, and outputs the one-bit shifted fraction number to the output register.
The floating point arithmetic circuit also includes an exponent correction circuit adapted to receive the data of the exponent portion from the adjustment circuit. The exponent correction circuit outputs the received exponent data as it is to an exponent portion of the output register when the overflow signal is not generated by the fraction operating circuit. But, when the overflow signal is generated, the exponent correction circuit adds "1" to the received exponent data and outputs the "1"-plused exponent data to the exponent portion of the output register.
In the arithmetic operation, however, not only floating point numbers are used, but also fixed point numbers are often to be operated, particularly in a signal processing frequently executing numerical data computation. In such a case, it is desired that not only floating point numbers but also fix point numbers can be processed in the same one device, microcomputer, and processor.
When the fixed point data is processed, the result of the arithmetic operation is outputted as it is without being corrected by an overflow resulting from the arithmetic operation. In the conventional floating point arithmetic circuit as described hereinbefore, however, when an overflow occurs from the arithmetic operation of fractions of the given numbers, the result of the arithmetic operation will be corrected without exception. In other words, the conventional floating point arithmetic cannot be used for the arithmetic operation of fixed point data.